1. Field of the Invention
The present invention relates to a semiconductor memory device which has a redundant memory cell.
2. Description of the Related Art
A DRAM (Dynamic Random Access Memory) has a problem of a yield decreasing, causing a defective memory cell. Recently, for increasing the yield, a redundant memory cell array for saving the defective memory cell has been used in the DRAM.
An address of the defective memory cell is detected by a test that includes writing data to each of the memory cells and reading the data from each of the memory cells.
When the address of a defective memory cell is detected, the address is programmed in a fuse ROM (Read Only Memory) which is included in a redundant judgment circuit. When the memory cell array is accessed from an external device, the redundant judgment circuit which is programmed with the defective address information judges whether or not the defective memory cell is accessed. If the accessing is performed to the defective memory cell, the accessing to the memory cell array which includes the defective memory cell is changed to accessing a redundant memory cell array by the redundant judgment circuit. As a result, the semiconductor memory device which includes the defective memory cell can be operated as a normal product.
Recently, it is needed to reduce power consumption in the DRAM. A technique for reducing power consumption is disclosed in Japanese Patent Laid-Open No. 11-168143.
The reference discloses a semiconductor memory device which has a plurality of redundant circuits. Each redundant circuit includes a fuse for redundant operation and a fuse for preventing a pass through current, and one of the fuses is cut. Accordingly, the pass through current is prevented, and the power consumption in the semiconductor device is reduced.
In a semiconductor memory device for high-speed operation such as a synchronous DRAM, the memory cell array is divided into a plurality of blocks and each block is accessed independently. The redundant memory cell array and the redundant judgment circuit are provided in each block.
The reference discloses a technique for reducing the power consumption in the redundant judgment circuit in the synchronous DRAM. However, the technique cannot be applied with a semiconductor memory device which has a plurality of memory cell blocks and a plurality of redundant judgment circuits.
A scheme for reducing the power consumption in the redundant judgment circuits in the respective blocks is needed for reducing the power consumption of the semiconductor memory device.